24-34 GHz Ka-Band Low Noise Amplifier

Commercial use (1):

For commercial use, with no derating, the CGY2128UH/C2 must be used as follows:

• • VDD1=VDD2=VDD3=+3.5V.
  • VSS1, VSS2, and VSS3 tuned to reach the nominal DC currents of 8mA, 13mA and
  • VDD2_S and VDD3_S left open (noconnection).

Space use (2):

For space use, including derating, the CGY2128UH/C2 must be used as follows:

• • VDD1=VDD2_S=VDD3_S=+3.5V.
  • VSS1, VSS2, and VSS3 tuned to reach the nominal DC currents of 8mA, 13mA and
  • VDD2 and VDD3 left open (noconnection).

In these conditions, no additional derating on biasing voltage or current has to be applied, the derating is build-in the circuit. Using the VDD2_S and VDD3_S pads applies automatically the correct deratings to the individual transistors through internal voltage drop resistors.

Typical application scheme:

A reference device environment layout is proposed below. In this figure 1, RF input and output microstrip transmission lines are used, but coplanar transmission lines with similar performance may also be used. All path lengths and physical sizes of the components should be minimized.

RF input bonding inductances should be minimized to give the best performance. Overall wire length should be kept as small as possible to reduce parasitic inductance. Higher RF input / output inductance may result in a degradation of gain and match. Ribbon bonding technique can also be used. The target inductance at the input is 0.08nH, corresponding to 2 wires of 180um length.

RF output bonding inductances should be minimized to give the best performance. Overall wire length should be kept as small as possible to reduce parasitic inductance. Higher RF input / output inductance may result in a degradation of gain and match. Ribbon bonding technique can also be used. The target inductance at the output is 0.15nH, corresponding to 1 wire of 180um length.

All others bonding inductances (pads V_DD1, V_DD2, V_{DD2_S}, V_DD3, V_{DD3_S} and V_ss1, V_ss2, V_ss3) should be kept as short as possible.

Decoupling 47 pF chip capacitors (close to the chip) and 10 nF chip capacitors are used to improve the power supply rejection. High value, additional decoupling capacitor in SMD format can be added

The chip itself has via holes connecting the front side to the back side of the chip. A good RF grounding connection should be maintained between the backside of the chip and system ground. It is extremely important to use an uninterrupted ground plane. AuSn eutectic soldering or silver conductive epoxy material can be used for die attachment.

Figure 1: CGY2128UH/C2 commercial application mounting scheme

Figure 2: CGY2128UH/C2 Space application mounting scheme

The CGY2128UH/C2 is very high performance MHEMT device and as such, care must be taken at all times to avoid damage due to inappropriate handling, mounting, packaging and biasing conditions.

1- Power Supply Sequence

The following power supply sequences are recommended:

 Power up

1. 1. Make sure the transient peaks from DC supply voltages do not exceed the limiting
   2. Set VDD1 ,V_DD2 (or V_DD2S) and V_DD3 (or V_DD3S) to0V
   3. Pinch off the device by setting V_ss1, V_ss2, V_ss3 to –1 V (gate current must be near 0mA).
   4. Increase V_DD1 ,V_DD2 (or V_DD2S) and V_DD3 (or V_DD3S) to 3.5V (drain current must stay near 0mA)
   5. Increase the gate voltages V_SS1, V_SS2 and V_SS3 slowly from –1 V until the three drains current stages reaches respectively 8mA, 13mA and 25mA.
   6. Apply the RF input

   Power down

1. 1. Remove RF input signal
   2. Pinch off the device by setting V_ss1, V_ss2, V_ss3 to –1 V (gate and drain current must be near 0mA).
   3. Set V_DD1 ,V_DD2 (or V_DD2S) and V_DD3 (or V_DD3S) to0V
   4. Set V_SS1, V_SS2 and V_SS3 to0V

2- Mounting and ESD handling precautions

For high performance Integrated Circuits, such as CGY2128UH/C2, care must be taken when mounting GaAs MMICs so as to correctly mount, bond and subsequently seal the packages and hence obtain the most reliable long-term operation. The temperature, duration, material and sealing techniques compatible with GaAs MMICs and the precautions to be taken are described in OMMIC’s document “OM-CI- MV/001/PG”, entitled, “Precautions for use III-V products”.